pin functions address inputs a0 - a17 data input/output d0 - d31 chip select input cs1- cs4 read/write input we output enable input oe power (+5v) v cc ground gnd pin definition block diagram description features the sys32256 is a plastic 8m static ram module offered in 64 pin zip and 64 lead simm package, organised as 256k x 32. the module utilises eight very fast srams housed in soj packages, and uses double sided surface mount techniques, to achieve a very high density module. four chip selects are used to independently enable the four bytes. reading or writing is executed on individual or any combination of multiple bytes. two pins pd0 & pd1 are used to identify module memory density where alternative versions of the jedec standard modules can be interchanged. ? access times of 020/25/30/35 ns. ? 64 pin zip & simm jedec standard pinouts. ? 5 volt supply 10%. ? power dissipation 35ns: operating (32bit mode) 6.60 w (maximum). standby (cmos) -l 4.40 mw (maximum). ? completely static operation. ? equal access and cycle times. ? all inputs and outputs directly ttl compatible. ? on-board supply decoupling capacitors. d0-d3 d8-d11 d16-d19 d24-d27 d4-d7 d12-d15 d20-d23 d28-d31 a0-a17 oe we cs1 cs2 cs3 cs4 256k x4 256k x4 256k x4 256k x4 256k x4 256k x4 256k x4 256k x4 cs3 a16 gnd d16 d17 d18 d19 a10 a11 a12 a13 d20 d21 d22 d23 gnd pd0 d0 d1 d2 d3 vcc a7 a8 a9 d4 d5 d6 d7 we a14 cs1 gnd pd1 d8 d9 d10 d11 a0 a1 a2 d12 d13 d14 d15 gnd a15 cs2 cs4 a17 oe d24 d25 d26 d27 a3 a4 a5 vcc a6 d28 d29 d30 d31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 256k x 32 sram module issue 1.7 : january 1999 sys32256zk/lk - 020/25/30/35 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
issue 1.7 january 1999 sys32256zk/lk - 020/25/30/35 2 parameter symbol test condition min typ max unit i/p leakage current i li v in = gnd to v cc, v cc =max. - - 16 a output leakage current i lo cs = v ih, v i/o = gnd to v cc - - 16 a average supply current (20/25/30) i cc1 t cyc = 20ns, cs = v il , v in = v il /v cc -2.1v - - 1440 ma average supply current (35/45/55) i cc2 t cyc = 35ns, cs= v il , v in =v il /v cc -2.1v - - 1200 ma standby supply current ttl levels i sb1 cs = v cc -2.1v, v il > v in > v cc -2.1v - - 320 ma cmos levels i sb2 cs = v cc -0.2v, 0.2 > v in > v cc -0.2v - 3.20 16 ma output low voltage v ol i ol = 8.0ma - - 0.4 v output high voltage v oh i oh = -4.0ma 2.4 - - v typical values are at v cc =5.0v,t a =25 c and specified loading. all values specified for 32 bit operation. i sb2 = 0.8ma max. for low power option. dc operating conditions absolute maximum ratings (1) recommended operating conditions parameter symbol min typ max unit voltage on any pin relative to v ss v t -0.5v - +7.0 v power dissipation p t - 4.0 - mw storage temperature t stg -55 - +125 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - 6.0 v input low voltage v il -0.3 - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i) dc electrical characteristics (v cc =5v10%) t a 0 to 70 o c
sys32256zk/lk - 020/25/30/35 issue 1.7 january 1999 3 low v cc data retention characteristics - l version only (t op = 0c to 70c) -l part parameter symbol test condition min typ (1) max unit v cc for data retention v dr cs - v cc -0.2v 2.0 - - v 0.2v 3 v in 3 v cc -0.2 data retention current i ccdr v cc = 3.0v, cs = v cc -0.2v - 16 400 m a 0.2v 3 v in 3 v cc -0.2 chip deselect to data retention time t cdr see retention waveform 0- - ns operation recovery time t r see retention waveform 5- - ms notes (1) typical figures are measured at 25c. parameter symbol test condition typ max unit input capacitance (cs) c in1 v in = 0v - 12 pf input capacitance (other) c in2 v in = 0v - 48 pf i/o capacitance c i/o v i/o = 0v - 8 pf capacitance (v cc =5v10%,t a =25 o c) note: capacitance calculated, not measured. ac test conditions output load * input pulse levels: vss to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc = 5v 10% csn oe we data pins supply current mode h x x high impedance i sb1 , i sb2 standby l l h data out i cc1 , i cc2 read l x l data in i cc1 , i cc2 write (1) l l l data in i cc1 , i cc2 write (2) notes : h = v ih : l =v il : x = v ih or v il operation truth table 166w 30pf i/o pin 1.76v
issue 1.7 january 1999 sys32256zk/lk - 020/25/30/35 4 read cycle (1,2) ac operating conditions -020 -25 -30 -35 parameter symbol min max min max min max min max unit read cycle time t rc 20 - 25 - 30 - 35 - ns address access time t aa -20-25-30-35ns chip select access time t acs -20-25-30-35ns output enable to output valid t oe -10-13-15-20ns output hold from address change t oh 3-3-3-3-ns chip selection to output in low z t clz 3-3-3-3-ns output enable to output in low z t olz 0-0-0-0-ns chip deselection to o/p in high z t chz 012015015020ns output disable to output in high z t ohz 010010012020ns -020 -25 -30 -35 parameter symbol min max min max min max min max unit write cycle time t wc 20 - 25 - 30 - 35 - ns chip selection to end of write t cw 17 - 20 - 25 - 30 - ns address setup time t as 0-0-0-0-ns address valid to end of write t aw 15 - 20 - 25 - 30 - ns write pulse width t wp 15 - 20 - 22 - 25 - ns write recovery time t wr 0-0-0-0-ns write to output in high z (3) t whz 0 8 0 10 0 12 0 15 ns data to write time overlap t dw 12 - 15 - 18 - 20 - ns data hold from write time t dh 0-0-0-0 -ns output active from end of write t ow 0-0-0-0-ns write cycle
sys32256zk/lk - 020/25/30/35 issue 1.7 january 1999 5 read cycle timing waveform (1,2) write cycle no.1 timing waveform ohz olz aa acs clz oe oh chz data valid t t t t t t t t t rc address cs dout oe don't care. dw dh wp as aw cw don't care t t t t t t t t t wc wr ohz address oe cs we dout din (6) high-z high-z ow t
issue 1.7 january 1999 sys32256zk/lk - 020/25/30/35 6 cw wr wc as dw dh oh ow whz aw wp don't t t t t t t address cs we dout din t t t t t care hi g h-z hi g h-z data retention waveform write cycle no.2 timing waveform t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs v dr cs > vcc -0.2v ac characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (4) module is continuously selected with cs = v il . (5) address is valid prior to or coincident with cs transition low. (6) a write occurs during the overlap (t wp ) of a low cs and a low we. (7) all write cycle timing is referenced from the last valid address to the first transition address. (8) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. (9) at any given temperature and voltage condition, t whz (max) is less than t ow (min) both for a given module and from module to module. (10) cs or we must be high during address transition.
sys32256zk/lk - 020/25/30/35 issue 1.7 january 1999 7 sys32256zkli - 30 speed 020 = 20 ns 25 = 25 ns 30 = 30 ns 35 = 35 ns temperature range blank = commercial temperature i = industrial temperature power rating blank = standard l = low power package zk = plastic 64 pin jedec zip lk = plastic 64 pin jedec simm organization 32256 = 256k x 32 memory type sys = static ram package information 64 pin zip 97.92 91.03 48.90 10.16 15.24 8.89 64 lead simm 8.89 92.71 15.49 max 3.80 min 2.54 2.54 pin 1 6.35 dimensions in mm. ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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